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integrated silicon solution, inc. ? 1-800-379-4774 1 rev. 00b 07/24/03 is64lf6436 is64lf6432 issi ? copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. features ? internal self-timed write cycle individual byte write control and global write clock controlled, registered address, data and control interleaved or linear burst sequence control using mode input three chip enables for simple depth expansion and address pipelining common data inputs and data outputs power-down control by zz input jedec 100-pin tqfp package power supply: +3.3v v dd +3.3v or 2.5v v ddq control pins mode upon power-up: ? mode in interleave burst mode ? zz in normal operation mode temperature offerings: option a1: -40 0 c to +85 0 c option a2: -40 0 c to +105 0 c option a3: -40 0 c to +125 0 c description the issi is64lf6432 and is64lf6436 are high-speed, low-power synchronous static ram designed to provide a burstable, high-performance, memory. is64lf6432 is orga- nized as 65,536 words by 32 bits and is64lf6436 is organized as 65,536 words by 36 bits. they are fabricated with issi 's advanced cmos technology. the device inte- grates a 2-bit burst counter, high-speed sram core, and high-drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. write cycles are internally self-timed and are initiated by the rising edge of the clock input. write cycles can be from one to four bytes wide as controlled by the write control inputs. separate byte enables allow individual bytes to be written. bw1 controls dq1-dq8, bw2 controls dq9-dq16, bw3 controls dq17-dq24, bw4 controls dq25-dq32, condi- tioned by bwe being low. a low on gw input would cause all bytes to be written. bursts can be initiated with either adsp (address status processor) or adsc (address status cache controller) input pins. subsequent burst addresses can be generated internally by the is64lf6432/36 and controlled by the adv (burst address advance) input pin. the mode pin is used to select the burst sequence order. linear burst is achieved when this pin is tied low. inter- leave burst is achieved when this pin is tied high or left floating. 64k x 32, 64kx36 synchronous flow-through static ram preliminary information august 2003 fast access time symbol parameter 8.5 10 unit t kq clock access time 8.5 10 ns t kc cycle time 11 15 ns frequency 90 66 mhz
is64lf6432 is64lf6436 issi ? 2 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 07/24/03 block diagram 16 binary counter a bw1 (x32/x36) gw clr ce clk q0 q1 mode a0' a0 a1 a1' clk adv adsc adsp 14 16 address register ce d clk q dq32-dq25 byte write registers d clk q dq24-dq17 byte write registers d clk q dq16-dq9 byte write registers d clk q dq8-dq1 byte write registers d clk q enable register ce d clk q enable delay register d clk q bwe bw4 (x32/x36) ce ce2 ce2 bw2 (x32/x36) bw3 (x32/x36) 64kx32 / 64kx36 memory array 32 or 36 input registers clk 32 or 36 oe 4 32 or 36 oe data[32:1]
is64lf6432 is64lf6436 issi ? integrated silicon solution, inc. ? 1-800-379-4774 3 rev. 00b 07/24/03 pin configuration pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bw1 - bw4 individual byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2 , ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode bu rst sequence mode selection v dd +3.3v power supply gnd ground v ddq isolated output buffer supply: +3.3v or 2.5v zz snooze enable nc dqb dqb vddq gnd dqb dqb dqb dqb gnd vddq dqb dqb gnd nc vdd zz dqa dqa vddq gnd dqa dqa dqa dqa gnd vddq dqa dqa nc a a ce ce2 bw4 bw3 bw2 bw1 ce2 vdd gnd clk gw bwe oe ads c adsp adv a a nc dqc dqc vddq gnd dqc dqc dqc dqc gnd vddq dqc dqc nc vdd nc gnd dqd dqd vddq gnd dqd dqd dqd dqd gnd vddq dqd dqd nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc gnd vdd nc nc a a a a a a nc 46 47 48 49 50 64k x 32 100-pin tqfp
is64lf6432 is64lf6436 issi ? 4 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 07/24/03 pin configuration pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bw1 - bw4 individual byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2 , ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection v dd +3.3v power supply gnd ground v ddq isolated output buffer supply: +3.3v or 2.5v zz snooze enable dqpa-dqpd parity data i/o dqpb dqb dqb vddq gnd dqb dqb dqb dqb gnd vddq dqb dqb gnd nc vdd zz dqa dqa vddq gnd dqa dqa dqa dqa gnd vddq dqa dqa dqpa a a ce ce2 bw4 bw3 bw2 bw1 ce2 vdd gnd clk gw bwe oe ads c adsp adv a a dqpc dqc dqc vddq gnd dqc dqc dqc dqc gnd vddq dqc dqc nc vdd nc gnd dqd dqd vddq gnd dqd dqd dqd dqd gnd vddq dqd dqd dqpd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode a a a a a1 a0 nc nc gnd vdd nc nc a a a a a a nc 46 47 48 49 50 64k x 36 100-pin tqfp
is64lf6432 is64lf6436 issi ? integrated silicon solution, inc. ? 1-800-379-4774 5 rev. 00b 07/24/03 truth table address operation used ce ce ce ce ce ce2 ce2 ce2 ce2 ce2 ce2 adsp adsp adsp adsp adsp adsc adsc adsc adsc adsc adv adv adv adv adv write write write write write oe oe oe oe oe dq deselected, power-down none h x x x l x x x high-z deselected, power-down none l x h l x x x x high-z deselected, power-down none l l x l x x x x high-z deselected, power-down none x x h h l x x x high-z deselected, power-down none x l x h l x x x high-z read cycle, begin burst external l h l l x x x x q read cycle, begin burst external l h l h l x read x q write cycle, begin burst external l h l h l x write x d read cycle, continue burst next x x x h h l read l q read cycle, continue burst next x x x h h l read h high-z read cycle, continue burst next h x x x h l read l q read cycle, continue burst next h x x x h l read h high-z write cycle, continue burst next x x x h h l w rite x d write cycle, continue burst next h x x x h l w rite x d read cycle, suspend burst current x x x h h h read l q read cycle, suspend burst current x x x h h h read h high-z read cycle, suspend burst current h x x x h h read l q read cycle, suspend burst current h x x x h h read h high-z write cycle, suspend burst current x x x h h h w rite x d write cycle, suspend burst current h x x x h h w rite x d partial truth table function gw gw gw gw gw bwe bwe bwe bwe bwe bw1 bw1 bw1 bw1 bw1 bw2 bw2 bw2 bw2 bw2 bw3 bw3 bw3 bw3 bw3 bw4 bw4 bw4 bw4 bw4 read h h xxxx read h l hhhh write byte 1 h l l h h h write all bytes h lllll write all bytes l xxxxx
is64lf6432 is64lf6436 issi ? 6 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 07/24/03 interleaved burst address table (mode = v dd or no connect) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 absolute maximum ratings (1) symbol parameter value unit t stg storage temperature ?55 to +150 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to gnd for i/o pins ?0.5 to v ddq + 0.3 v v in voltage relative to gnd for ?0.5 to v dd + 0.5 v for address and control inputs v dd voltage on v dd supply relative to gnd ?0.5 to 4.6 v notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. 0,0 1,0 0,1 a1', a0' = 1,1
is64lf6432 is64lf6436 issi ? integrated silicon solution, inc. ? 1-800-379-4774 7 rev. 00b 07/24/03 operating range 3.3v (i/o) 2.5v (i/o) range ambient temperature v dd v ddq v ddq a1 ?40c to +85c 3.3v, +10%, ?5% 3.3v, +10%, ?5% 2.5v + 5% a2 ?40c to +105c 3.3v, +10%, ?5% 3.3v, +10%, ?5% 2.5v + 5% a3 ?40c to +125c 3.3v, +10%, ?5% 3.3v, +10%, ?5% 2.5v + 5% dc electrical characteristics (1) (over operating range) 2.5v (i/o) 3.3v (i/o) symbol parameter test conditions min. max. min. max. unit v oh output high voltage i oh = ?4.0 ma (3.3v) 2.0 ? 2.4 ? v i oh = 1.0 ma (2.5v) v ol output low voltage i ol = 8.0 ma (3.3v) ? 0.4 ? 0.4 v i ol = 1.0 ma (2.5v) v ih input high voltage 1.7 v dd + 0.3 2.0 v dd + 0.3 v v il input low voltage ?0.3 0.7 ?0.3 0.8 v i li input leakage current gnd v in v dd ?5 5 ?5 5 a i lo output leakage current gnd v out v ddq ,?5 5 ?5 5 a oe = v i power supply characteristics (over operating range) 8.5 10 symbol parameter test conditions max. max. uni t i cc ac operating device selected, a1 180 ? ma supply current all inputs = v il or v ih a2 190 ? ma oe = v ih , v dd = max. a3 ? 190 ma cycle time t kc min. i sb standby current device deselected, a1 70 ? ma v dd = max., a2 80 ? ma all inputs = v ih or v il a3 ? 90 ma clk cycle time t kc min. i zz power-down mode zz = v dd a1 15 ? ma current clock running a2 20 ? ma all inputs gnd + 0.2v a3 ? 30 ma or v dd ? 0.2v notes: 1. the mode pin has an internal pullup. this pin may be a no connect, tied to gnd, or tied to v dd . 2. the mode pin should be tied to v dd or gnd. it exhibits 10 a maximum leakage current when tied to gnd + 0.2v or v dd ? 0.2v.
is64lf6432 is64lf6436 issi ? 8 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 07/24/03 capacitance (1,2) symbol parameter cond itions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v. 3.3v i/o ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 1.5 ns input and output timing 1.5v and reference level output load see figures 1 and 2 output z o = 50 ? 1.5v 50 ? 317 ? 5 pf including jig and scope 351 ? output +3.3v figure 1 figure 2 3.3v i/o output load equivalent
is64lf6432 is64lf6436 issi ? integrated silicon solution, inc. ? 1-800-379-4774 9 rev. 00b 07/24/03 2.5v i/o ac test conditions parameter unit input pulse level 0v to 2.5v input rise and fall times 1ns input and output timing 1.25v and reference level output load see figures 3 and 4 output z o = 50 ? 1.25v 50 ? 1,667 ? 5 pf including jig and scope 1538 ? output +2.5v figure 3 figure 4 2.5v i/o output load equivalent
is64lf6432 is64lf6436 issi ? 10 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 07/24/03 read/write cycle switching characteristics (over operating range) 8.5 10 symbol p arameter min. max. min. max. unit f max (3) clock frequency ? 90 ? 66 mhz t kc (3) cycle time 11 ? 15 ? ns t kh clock high time 4.5 ? 4.5 ? ns t kl (3) clock low time 4.5 ? 4.5 ? ns t kq (3) clock access time ? 8.5 ? 10 ns t kqx (1) clock high to output invalid 2 ? 2 ? ns t kqlz (1,2) clock high to output low-z 0 ? 0 ? ns t kqhz (1,2) clock high to output high-z 2 3.5 2 3.5 ns t oeq (3) output enable to output valid ? 4.0 ? 4.0 ns t oelz (1,2) output enable to output low-z 0 ? 0 ? ns t oehz (1,2) output disable to output high-z ? 5.0 ? 5.0 ns t as (3) address setup time 2 ? 2 ? ns t ss (3) address status setup time 2 ? 2 ? ns t ws (3) write setup time 2 ? 2 ? ns t ces (3) chip enable setup time 2 ? 2 ? ns t avs (3) address advance setup time 2 ? 2 ? ns t ah (3) address hold time 1 ? 1 ? ns t sh (3) address status hold time 0.5 ? 0.5 ? ns t wh (3) write hold time 0.5 ? 0.5 ? ns t ceh (3) chip enable hold time 0.5 ? 0.5 ? ns t avh (3) address advance hold time 0.5 ? 0.5 ? ns notes: 1. guaranteed but not 100% tested. this parameter is periodically sampled. 2. tested with load in figure 2. 3. tested with load in figure 1.
is64lf6432 is64lf6436 issi ? integrated silicon solution, inc. ? 1-800-379-4774 11 rev. 00b 07/24/03 read/write cycle timing single read flow-through single write high-z high-z data out data in oe ce2 ce2 ce bw4 - bw1 bwe gw a adv adsc adsp clk rd1 wr1 wr1 1a 1a 2a 2b 2c 2d unselected burst read t kqx t kc t kl t kh t ss t sh adsp is blocked by ce inactive t ss t sh t as t ah t ws t wh t ws t wh t ws t wh rd2 rd3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 t oeqx t kq t oehz t kqx t kqhz t ds t dh t kqhz t kqlz
is64lf6432 is64lf6436 issi ? 12 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 07/24/03 write cycle switching characteristics (over operating range) 8.5 10 symbol parameter min. max. min. max. unit t kc (1) cycle time 11 ? 15 ? ns t kh (1) clock high time 4.5 ? 4.5 ? ns t kl (1) clock low time 4.5 ? 4.5 ? ns t as (1) address setup time 2 ? 2 ? ns t ss (1) address status setup time 2 ? 2 ? ns t ws (1) write setup time 2 ? 2 ? ns t ds (1) data in setup time 3 ? 3 ? ns t ces (1) chip enable setup time 2 ? 2 ? ns t avs (1) address advance setup time 2 ? 2 ? ns t ah (1) address hold time 1 ? 1 ? ns t sh (1) address status hold time 0.5 ? 0.5 ? ns t dh (1) data in hold time 1 ? 1 ? ns t wh (1) write hold time 0.5 ? 0.5 ? ns t ceh (1) chip enable hold time 0.5 ? 0.5 ? ns t avh (1) address advance hold time 0.5 ? 0.5 ? ns notes: 1. tested with load in figure 1.
is64lf6432 is64lf6436 issi ? integrated silicon solution, inc. ? 1-800-379-4774 13 rev. 00b 07/24/03 write cycle timing single write data out data in oe ce2 ce2 ce bw4 - bw1 bwe gw a adv adsc adsp clk wr1 wr2 unselected burst write t kc t kl t kh t ss t sh t as t ah t ws t wh t ws t wh wr3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 adsc initiate write adsp is blocked by ce inactive t avh t avs adv must be inactive for adsp write wr1 wr2 t ws t wh wr3 t ws t wh high-z high-z 1a 3a t ds t dh bw4-bw1 only are applied to first cycle of wr2 write 2c 2d 2b 2a
is64lf6432 is64lf6436 issi ? 14 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 07/24/03 snooze and recovery cycle switching characteristics (over operating range) 8.5 10 symbol parameter min. max. min. max. unit t kc (3) cycle time 11 ? 15 ? ns t kh (3) clock high time 4.5 ? 4.5 ? ns t kl (3) clock low time 4.5 ? 4.5 ? ns t kq (3) clock access time ? 8.5 ? 10 ns t kqx (1) clock high to output invalid 2 ? 2 ? ns t kqlz (1,2) clock high to output low-z 0 ? 0 ? ns t kqhz (1,2) clock high to output high-z 2 3.5 2 3.5 ns t oeq (3) output enable to output valid ? 4.0 ? 4.0 ns t oelz (1,2) output enable to output low-z 0 ? 0 ? ns t oehz (1,2) output disable to output high-z ? 5.0 ? 5.0 ns t as (3) address setup time 2 ? 2 ? ns t ss (3) address status setup time 2 ? 2 ? ns t ces (3) chip enable setup time 2 ? 2 ? ns t ah (3) address hold time 1.0 ? 1.0 ? ns t sh (3) address status hold time 0.5 ? 0.5 ? ns t ceh (3) chip enable hold time 0.5 ? 0.5 ? ns t zzs zz standby 2 ? 2 ? cyc t zzrec zz recovery 2 ? 2 ? cyc notes: 1. guaranteed but not 100% tested. this parameter is periodically sampled. 2. tested with load in figure 2. 3. tested with load in figure 1.
is64lf6432 is64lf6436 issi ? integrated silicon solution, inc. ? 1-800-379-4774 15 rev. 00b 07/24/03 snooze and recovery cycle timing single read high-z high-z data out data in oe ce2 ce2 ce bw4 - bw1 bwe gw a adv adsc adsp clk rd1 1a read snooze with data retention t kc t kl t kh t ss t sh t as t ah rd2 t ces t ceh t ces t ceh t ces t ceh t oeq t oeqx t oelz t kqlz t kq t oehz t kqx t kqhz zz t zzs t zzrec
is64lf6432 is64lf6436 issi ? 16 integrated silicon solution, inc. ? 1-800-379-4774 rev. 00b 07/24/03 ordering information is64lf6432 (3.3v i/o or 2.5v i/o) temperature range (a1): -40c to +85c speed (ns) order part no. package 8.5 is64lf6432-8.5tq a1 tqfp 8.5 is64lf6436-8.5tq a1 tqfp temperature range (a2): -40c to +105c speed (ns) order part no. package 8.5 is64lf6432-8.5tq a2 tqfp 8.5 is64lf6436-8.5tq a2 tqfp temperature range (a3): -40c to +125c speed (ns) order part no. package 10 is64lf6432- 10tqa3 tqfp 10 is64lf6436- 10tqa3 tqfp
integrated silicon solution, inc. ? 1-800-379-4774 packaging information issi ? pk13197lq rev. d 05/08/03 tqfp (thin quad flat pack package) package code: tq thin quad flat pack (tq) millimeters inches millimeters inches symbol min max min max min max min max ref. std. no. leads (n) 100 128 a ? 1.60 ? 0.063 ? 1.60 ? 0.063 a1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 a2 1.35 1.45 0.053 0.057 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 0.17 0.27 0.007 0.011 d 21.90 22.10 0.862 0.870 21.80 22.20 0.858 0.874 d1 19.90 20.10 0.783 0.791 19.90 20.10 0.783 0.791 e 15.90 16.10 0.626 0.634 15.80 16.20 0.622 0.638 e1 13.90 14.10 0.547 0.555 13.90 14.10 0.547 0.555 e 0.65 bsc 0.026 bsc 0.50 bsc 0.020 bsc l 0.45 0.75 0.018 0.030 0.45 0.75 0.018 0.030 l1 1.00 ref. 0.039 ref. 1.00 ref. 0.039 ref. c0 o 7 o 0 o 7 o 0 o 7 o 0 o 7 o notes: 1. all dimensioning and tolerancing conforms to ansi y14.5m-1982. 2. dimensions d1 and e1 do not include mold protrusions. allowable protrusion is 0.25 mm per side. d1 and e1 do include mold mismatch and are determined at datum plane -h-. 3. controlling dimension: millimeters. d d1 e e1 1 n a2 a a1 e b seating plane c l1 l

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